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@INPROCEEDINGS{3D:Canegallo08,
  author = {Canegallo, R. and Ciccarelli, L. and Natali, F. and others},
  title = {3D Contactless communication for IC design},
  booktitle = {Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT
	2008. IEEE International Conference on},
  year = {2008},
  pages = {241-244},
  month = {June},
  abstract = {3D contactless technology based on capacitive coupling represents
	a promising solution for high-speed and low power signaling in vertically
	integrated chips. AC coupled interconnects do not suffer from mechanical
	stress, and the parasitic load is much reduced when compared to standard
	DC solutions, such as wire bonding and micro bumps. Communication
	system based on wireless interconnection scheme with transmitter
	and receiver circuits implemented in 0.13mum CMOS technology and
	connected to 8x8mum2 electrodes in the upper metal layer of different
	dies and with face-to-face assembly, makes available a throughput
	of more than 22Mbps/mum2 with 80muW/Gbps energy consumption.},
  doi = {10.1109/ICICDT.2008.4567286},
  file = {:D\:\\paper\\NoC\\2008-ICSCDT-Canegallo-3D Contactless Communication for IC Design.pdf:PDF},
  keywords = {coupled circuits, integrated circuit design, integrated circuit interconnections3D
	contactless communication, AC coupled interconnects, CMOS technology,
	IC design, capacitive coupling, face-to-face assembly, micro bumps,
	parasitic load, vertically integrated chips, wire bonding, wireless
	interconnection scheme},
  owner = {Jin Ouyang},
  timestamp = {10.23.2009}
}

@INPROCEEDINGS{reetuhpca08,
  author = {Das, R. and Mishra, A.K. and Nicopoulos, C. and others},
  title = {{Performance and power optimization through data compression in Network-on-Chip
	architectures}},
  booktitle = {Proc. of High Performance Computer Architecture},
  year = {2008},
  pages = {215-225},
  month = {Feb.},
  doi = {10.1109/HPCA.2008.4658641},
  issn = {1530-0897},
  keywords = {cache storage, data compression, network routing, network-on-chipNoC
	communication latency, NoC performance, cache compression, communication
	compression, data compression, energy behavior, network-on-chip architecture,
	nonuniform cache-based multicore architectures, on-chip cache, packet-based
	network-on-chip, power consumption, power optimization, router architecture,
	storage compression}
}

@INPROCEEDINGS{3D:FazziCap07,
  author = {Fazzi, A. and Canegallo, R. and Ciccarelli, L. and others},
  title = {{3D} Capacitive Interconnections with Mono- and Bi-Directional Capabilities},
  booktitle = {Proc. of Solid-State Circuits Conference},
  year = {2007},
  pages = {356-608},
  month = {Feb.},
  abstract = {A wireless interconnection scheme based on capacitive coupling provides
	mono- and bi-directional transmission capabilities for 3D system
	integration. Chips are implemented in 0.13mum CMOS and assembled
	face-to-face. RX-TX circuits are connected by 8times8mum 2 electrodes
	and this enables the vertical propagation of clock at 17GHz, a propagation
	delay of 420ps for general purpose signals and a throughput of more
	than 22Mb/s/mum2 with 0.08pJ/b energy consumption},
  doi = {10.1109/ISSCC.2007.373441},
  file = {:D\:\\paper\\NoC\\2007-ISSCC-3D capacitive interconnections.pdf:PDF},
  issn = {0193-6530},
  keywords = {CMOS integrated circuits, capacitors, coupled circuits, integrated
	circuit interconnections0.13 micron, 17 GHz, 3D capacitive interconnections,
	3D system integration, CMOS, RX-TX circuits, bi-directional capability,
	capacitive coupling, mono-directional capability, vertical propagation,
	wireless interconnection}
}

@INPROCEEDINGS{3D:capacitivecoup2007,
  author = {Qun Gu and Zhiwei Xu and Jenwei Ko and Mau-Chung Frank Chang},
  title = {{Two 10Gb/s/pin low-Power interconnect methods for 3D ICs}},
  booktitle = {{Proc. of Solid-State Circuits Conference}},
  year = {2007},
  pages = {448-614},
  month = {Feb.},
  abstract = {Two RF techniques are combined with capacitive coupling interconnect
	to form ultra-wide-bandwidth impulse interconnect and RF interconnect
	in 3D IC technology. They achieve 10Gb/s/pin and 11Gb/s/pin transmission
	with 2.7mW/pin and 4.35mW/pin power consumption, respectively, using
	the MIT Lincoln Lab 3D 0.18mum CMOS, an 8times improvement over previous
	work},
  doi = {10.1109/ISSCC.2007.373487},
  file = {:D\:\\paper\\NoC\\2007-ISSCC-Gu-Two 10Gbps Low-power Interconnect for 3D.pdf:PDF},
  issn = {0193-6530},
  keywords = {CMOS integrated circuits, integrated circuit design, integrated circuit
	interconnections, low-power electronics0.18 micron, 10 Gbit/s, 11
	Gbit/s, 2.7 mW, 3D integrated circuits, 4.35 mW, CMOS integrated
	circuit, RF interconnect, RF techniques, capacitive coupling interconnect,
	low-power interconnect methods, ultra-wide-bandwidth impulse interconnect},
  owner = {Jin Ouyang},
  timestamp = {10.22.2009}
}

@INPROCEEDINGS{3D:SUNCapacitive07,
  author = {Hopkins, D. and Chow, A. and Bosnyak, R. and others},
  title = {Circuit Techniques to Enable {430Gb/s/mm$^2$} Proximity Communication},
  booktitle = {Proc. of Solid-State Circuits Conference},
  year = {2007},
  pages = {368-609},
  month = {Feb.},
  abstract = {Two chips communicate over a capacitively-coupled I/O link at 1.8Gb/s/ch.
	Channels are placed on a 36mum pitch. 144 channels operate simultaneously
	for an aggregate bandwidth of 260Gb/s, or 430Gb/s/mm2 in 0.18mum
	CMOS. Measured energy consumption is 3.0pJ/b and BER is <10-15. Electronic
	alignment and crosstalk rejection allow reliable I/O for practical
	implementation},
  doi = {10.1109/ISSCC.2007.373447},
  file = {:D\:\\paper\\3D\\2007-ISSCC-SUN-Capacitive coupling.pdf:PDF},
  issn = {0193-6530},
  keywords = {CMOS integrated circuits, integrated circuit interconnections0.18
	micron, 36 micron, CMOS circuit, capacitively-coupled I/O link, circuit
	techniques, crosstalk rejection, electronic alignment, proximity
	communication},
  owner = {Jin Ouyang},
  timestamp = {10.23.2009}
}

@INPROCEEDINGS{3D:IshikuroAttach07,
  author = {Ishikuro, H. and Sugahara, T. and Kuroda, T.},
  title = {An Attachable Wireless Chip Access Interface for Arbitrary Data Rate
	Using Pulse-Based lnductive-Coupling through {LSI} Package},
  booktitle = {Proc. of Solid-State Circuits Conference},
  year = {2007},
  pages = {360-608},
  month = {Feb.},
  abstract = {A wireless logic-probing system is presented as one of the applications
	of the millimeter-range carrierless inductive-coupling technique.
	A pulse transceiver for a wireless probe and its target LSI is fabricated
	using a 0.25mum standard CMOS logic process. A maximum data rate
	of 20Mb/s and a communication range of 1.2mm is achieved.},
  doi = {10.1109/ISSCC.2007.373443},
  file = {:D\:\\paper\\NoC\\2007-ISSCC-Attachable inductive coupling.pdf:PDF},
  issn = {0193-6530},
  keywords = {CMOS logic circuits, integrated circuit packaging, large scale integration,
	transceivers0.25 micron, 20 Mbit/s, CMOS logic process, LSI package,
	arbitrary data rate, attachable wireless chip access interface, carrierless
	inductive-coupling technique, pulse transceiver, pulse-based inductive-coupling,
	wireless logic-probing system},
  owner = {Jin Ouyang},
  timestamp = {10.23.2009}
}

@INPROCEEDINGS{3D:capacitiveKawai10,
  author = {Kawai, S. and Ishikuro, H. and Kuroda, T.},
  title = {A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact
	memory card},
  booktitle = {Solid-State Circuits Conference Digest of Technical Papers (ISSCC),
	2010 IEEE International},
  year = {2010},
  pages = {264 -265},
  month = {7-11},
  doi = {10.1109/ISSCC.2010.5433947},
  issn = {0193-6530},
  keywords = {4PAM inductive-coupling transceiver;BER;automatic gain;bit rate 2.5
	Gbit/s;noncontact memory card;phase control;coupled circuits;error
	statistics;memory cards;phase control;pulse amplitude modulation;transceivers;}
}

@ARTICLE{3D:Miura014,
  author = {Miura, N. and Ishikuro, H. and Niitsu, K. and others},
  title = {A {0.14 pJ/b} Inductive-Coupling Transceiver With Digitally-Controlled
	Precise Pulse Shaping},
  journal = {Journal of Solid-State Circuits},
  year = {2008},
  volume = {43},
  pages = {285-291},
  number = {1},
  month = {Jan. },
  abstract = {A transceiver for inductive-coupling is realized. By using a pulse-shaping
	circuit, the transmitter energy is 0.11 pJ/b. Due to device scaling
	from 180 nm CMOS to 90 nm CMOS, the receiver energy is 0.03 pJ/b.
	The overall energy dissipation is 20X lower than previous work, without
	degrading the data rate of 1 Gb/s.},
  doi = {10.1109/JSSC.2007.914716},
  file = {:D\:\\paper\\optical\\JSSC08-Miutra-0.14pjs Inductive Coupling Transceiver.pdf:PDF},
  issn = {0018-9200},
  keywords = {digital control, pulse shaping circuits, transceiversdigitally-controlled
	precise pulse shaping, energy dissipation, inductive-coupling transceiver},
  owner = {Jin Ouyang},
  timestamp = {10.23.2009}
}

@INPROCEEDINGS{3D:Miura11Gb,
  author = {Miura, N. and Kohama, Y. and Sugimori, Y. and Ishikuro, H. and Sakurai,
	T. and Kuroda, T.},
  title = {An 11Gb/s Inductive-Coupling Link with Burst Transmission},
  booktitle = {Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical
	Papers. IEEE International},
  year = {2008},
  pages = {298-614},
  month = {Feb.},
  abstract = {An inductive-coupling link is presented whose data rate is 11Gb/s
	for a distance of 15mum and 8.5Gb/s for a distance of 45mum. The
	data rate is increased by 11 to 8.5x over past inductive-coupling
	links. Compared with the capacitive-coupling link (Cu et al., 2007),
	the communication distance is extended by 5x for the same data rate,
	layout area, and bit error rate (BER), even by using a less- scaled
	device technology, 0.18mum CMOS.},
  doi = {10.1109/ISSCC.2008.4523175},
  file = {:D\:\\paper\\NoC\\ISSCC08-Miura-11Gbs Inductive.pdf:PDF},
  keywords = {CMOS integrated circuits, error statistics, radio linksCMOS integrated
	circuit, bit error rate, bit rate 11 Gbit/s, bit rate 8.5 Gbit/s,
	burst transmission, communication distance, distance 15 mum, distance
	45 mum, inductive coupling link, less-scaled device technology, size
	0.18 mum},
  owner = {Jin Ouyang},
  timestamp = {10.23.2009}
}

@ARTICLE{3D:MiuraBurst,
  author = {Miura, N. and Kohama, Y. and Sugimori, Y. and others},
  title = {A High-Speed Inductive-Coupling Link With Burst Transmission},
  journal = {Solid-State Circuits, IEEE Journal of},
  year = {2009},
  volume = {44},
  pages = {947-955},
  number = {3},
  month = {March },
  abstract = {A high-speed inductive-coupling link is presented. It communicates
	at a data rate of 11 Gb/s for a communication distance of 15 mum
	in 180 nm CMOS. The data rate is 11times higher than previous inductive-coupling
	links. The communication distance is 5times longer than a capacitive-coupling
	link for the same data rate, bit error rate, and layout area. Burst
	transmission utilizing the high-speed inductive-coupling link is
	also presented. Multi-bit data links are multiplexed into a single
	burst data link. It reduces layout area by a factor of three in 180
	nm CMOS and a factor of nine in 90 nm CMOS.},
  doi = {10.1109/JSSC.2008.2012365},
  file = {:D\:\\paper\\NoC\\2009-JSSC-Miura-Inductive Burst.pdf:PDF},
  issn = {0018-9200},
  keywords = {CMOS integrated circuits, coupled circuits, integrated circuit interconnectionsburst
	transmission, high-speed inductive-coupling link, multi-bit data
	links},
  owner = {Jin Ouyang},
  timestamp = {10.23.2009}
}

@ARTICLE{3D:MizoguchiMIK08,
  author = {Daisuke Mizoguchi and Noriyuki Miura and Hiroki Ishikuro and Tadahiro
	Kuroda},
  title = {Constant Magnetic Field Scaling in Inductive-Coupling Data Link},
  journal = {IEICE Trans. on Electronics},
  year = {2008},
  volume = {91-C},
  pages = {200-205},
  number = {2},
  file = {:D\:\\paper\\NoC\\2008-IEICETE-Mizoguchi-Constant Magnetic Field Scaling.pdf:PDF},
  owner = {Jin Ouyang},
  timestamp = {10.23.2009}
}

@INPROCEEDINGS{3D:inductivemop09,
  author = {Niitsu, K. and Shimazaki, Y. and Sugimori, Y. and others},
  title = {{An inductive-coupling link for 3D integration of a 90nm CMOS processor
	and a 65nm CMOS SRAM}},
  booktitle = {Proc. of Solid-State Circuits Conference},
  year = {2009},
  pages = {480-481},
  month = {Feb.},
  abstract = {This paper presents a three-dimensional (3D) system integration of
	a commercial processor and a memory by using inductive coupling.
	A 90 nm CMOS 8-core processor, back-grinded to a thickness of 50
	mum, is mounted face down on a package by C4 bump. A 65 nm CMOS 1
	MB SRAM of the same thickness is glued on it face up, and the power
	is provided by conventional wire-bonding. The two chips under different
	supply voltages are AC-coupled by inductive coupling that provides
	a 19.2 Gb/s data link. Measured power and area efficiency of the
	link is 1 pJ/b and 0.15 mm2/Gbps, which is 1/30 and 1/3 in comparison
	with the conventional DDR2 interface respectively.},
  doi = {10.1109/ISSCC.2009.4977517},
  keywords = {CMOS memory circuits, SRAM chips, integrated circuit design, integrated
	circuit packagingCMOS 8-core processor 3D integration, CMOS SRAM
	chip, bit rate 19.2 Gbit/s, circuit package, inductive-coupling link,
	power measurement, size 50 mum, size 65 nm, size 90 nm, three-dimensional
	system integration}
}

@INPROCEEDINGS{3D:serialTSV09,
  author = {Pasricha, S.},
  title = {{Exploring serial vertical interconnects for 3D ICs}},
  booktitle = {Proc. of Design Automation Conference},
  year = {2009},
  pages = {581-586},
  month = {Jul.},
  abstract = {Three-dimensional integrated circuits (3D ICs) offer a promising solution
	to overcome the on-chip communication bottleneck and improve performance
	over traditional two-dimensional (2D) ICs. Long interconnects can
	be replaced by much shorter vertical through silicon via (TSV) interconnects
	in 3D ICs. This enables faster and more power efficient inter-core
	communication across multiple silicon layers. However, 3D IC technology
	also faces challenges due to higher power densities and routing congestion
	due to TSV pads distributed on each layer. In this paper, serialization
	of vertical TSV interconnects in 3D ICs is proposed as one way to
	address these challenges. Such serialization reduces the interconnect
	TSV footprint on each layer. This can lead to a better thermal TSV
	distribution resulting in lower peak temperatures, as well as more
	efficient core layout across multiple layers due to the reduced congestion.
	Experiments with several 3D multi-core benchmarks indicate clear
	benefits of serialization. For instance, a 4:1 serialization of TSV
	interconnects can save more than 70% of TSV area footprint at a negligible
	performance and power overhead at the 65 nm technology node.},
  file = {:D\:\\paper\\3D\\2009-DAC-Pasricha-Serial Link for 3D.pdf:PDF},
  issn = {0738-100X},
  keywords = {integrated circuit interconnections, integrated circuit layout, network
	routing, silicon3D IC serial vertical interconnects, core layout,
	integrated circuit layout, on-chip communication bottleneck, power
	efficient intercore communication, routing congestion, silicon layers,
	size 65 nm, three-dimensional integrated circuits, vertical through
	silicon via interconnects},
  owner = {Jin Ouyang},
  timestamp = {10.22.2009}
}

@ARTICLE{3D:inductiveSaen09,
  author = {Saen, M. and Osada, K. and Okuma, Y. and Niitsu, K. and Shimazaki,
	Y. and Sugimori, Y. and Kohama, Y. and Kasuga, K. and Nonomura, I.
	and Irie, N. and Hattori, T. and Hasegawa, A. and Kuroda, T.},
  title = {3-D System Integration of Processor and Multi-Stacked SRAMs Using
	Inductive-Coupling Link},
  journal = {Solid-State Circuits, IEEE Journal of},
  year = {2010},
  volume = {45},
  pages = {856 -862},
  number = {4},
  month = {april },
  doi = {10.1109/JSSC.2010.2040310},
  issn = {0018-9200},
  keywords = {3D communication link;3D system integration;SRAM;inductive coupling;inductive-coupling
	link;memory chips;memory-access-control scheme;pinpoint-data-capture
	scheme;processor chip;SRAM chips;microprocessor chips;}
}

@INPROCEEDINGS{3D:inductiveSaito10,
  author = {Saito, M. and Miura, N. and Kuroda, T.},
  title = {A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die
	NAND-Flash memory stacking},
  booktitle = {Solid-State Circuits Conference Digest of Technical Papers (ISSCC),
	2010 IEEE International},
  year = {2010},
  pages = {440 -441},
  month = {7-11},
  doi = {10.1109/ISSCC.2010.5433929},
  issn = {0193-6530},
  keywords = {NAND flash memory stacking;bit rate 2 Gbit/s;controller chip;inductive
	coupling through chip bus;random memory chip;spiral stair stacking;through
	chip transmission;NAND circuits;coupled circuits;flash memories;integrated
	circuit interconnections;system buses;}
}

@INPROCEEDINGS{3D:inductivexu05,
  author = {Jian Xu and Wilson, J. and Mick, S. and Lei Luo and Franzon, P.},
  title = {{2.8 Gb/s inductively coupled interconnect for 3D ICs}},
  booktitle = {Proc. of Symposium on VLSI Circuits},
  year = {2005},
  pages = { 352-355},
  month = {Jun.},
  doi = {10.1109/VLSIC.2005.1469403},
  issn = { },
  keywords = { CMOS integrated circuits, inductors, integrated circuit design, integrated
	circuit interconnections, transceivers, transformers 0.35 micron,
	100 ps, 150 micron, 2.8 Gbit/s, 3D integrated circuit, 90 micron,
	AC coupled interconnects, CMOS technology, NRZ signals, RX power
	dissipation, TX power dissipation, inductive coupling, inductors,
	integrated circuit interconnects, transceiver, transformer, vertical
	signaling}
}

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